1. Field of the Invention
The invention relates to a method of forming a twin-well for CMOS (Complementary Metal-Oxide-Semiconductor) transistors, and more particularly, to a method of forming a self-aligned planarization twin-well for CMOS transistors by using fewer mask counts than conventional skills.
2. Description of the Prior Art
In the present days, CMOS transistors construct more and more devices because the CMOS structures offer a lot of advantages such as low power consumption than NMOS and PMOS transistors. For example, the CMOS transistors draw very little current during the transition from one state to another, and allow power consumption to be minimized. However, the aforementioned advantages are important attributes for high-density applications.
Typically, there are many technologies used to fabricate the CMOS transistors, such as p-well, n-well, and twin-well processes. As noted, the twin-well process is the most attractive scheme utilized for fabricating CMOS products because many advantages offered by the twin-well technology. The twin-well technology fabricates two separate twins to be implemented into very lightly doped silicon. This also allows the doping profiles in each twin region to be tailored independently so that neither type of device will suffer from excessive doping effects. Furthermore, the doping profile of each of the device types can be set independently since the constraint of single-well CMOS does not exist.
All persons skilled in the art know that a planar surface should be prepared before performing sequence processes of forming CMOS transistors. Unfortunately, it is difficult to obtain a true planarized self-aligned twin-well for CMOS transistors because the twin boundary has a topography height, which usually varies from 100 to 200 nm (nano meters). Under this situation with such a topography height, the current I-line lithography tools encounter severe difficulties when printing transistors with dimension below 0.35 .mu.m. Accordingly, this disadvantage becomes a bottleneck especially for deep sub-micro ULSI (Ultra-Large-Scale-Integrated) applications that are the main electronic products today (please refer to "0.2-.mu.m n-Channel and p-Channel MOSFET's Integrated on Oxidation-Planarized Twin-Tubs" in IEEE Electron Device Lett., vol., EDL-11, p. 500-502, 1996.) Also, for gate runners parallel to the topography edges, ragged lines are formed due to proximity effects in the resist exposure. Therefore, for the lithography of deep sub-micro window contact that contains more topography from the gate runners, the variation becomes even more server. A requirement has been arisen to disclose a process for overcoming the aforementioned disadvantages while fabricating CMOS transistors.